000 -LEADER |
fixed length control field |
00796nam a2200217Ia 4500 |
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
161214s9999 xx 000 0 und d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781598294040 |
Terms of availability |
(hbk) |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
621.392 |
Item number |
REE |
100 ## - MAIN ENTRY--PERSONAL NAME |
Personal name |
Reese, Robert B. |
245 #0 - TITLE STATEMENT |
Title |
Introduction to logic synthesis using Verilog HDL |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
Place of publication, distribution, etc |
San Rafael: |
Name of publisher, distributor, etc |
Morgan & Claypool Publishers, |
Date of publication, distribution, etc |
2006 |
300 ## - PHYSICAL DESCRIPTION |
Extent |
vii, 75 p.; |
Other physical details |
ill.: |
Dimensions |
24 cm. |
490 ## - SERIES STATEMENT |
Series statement |
Synthesis lectures on digital circuits and systems, 6 |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Computer hardware description languages |
|
Topical term or geographic name as entry element |
Computer-aided design |
|
Topical term or geographic name as entry element |
Electronic digital computers -- Design and construction |
|
Topical term or geographic name as entry element |
Logic design -- Data processing |
|
Topical term or geographic name as entry element |
Verilog (Computer hardware description language) |
700 ## - ADDED ENTRY--PERSONAL NAME |
Personal name |
Thornton, Mitchell Aaron |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
Books |
952 ## - LOCATION AND ITEM INFORMATION (KOHA) |
-- |
083210 Morgan & Claypool Publishers |