Symbolic parallelization of ested loop programs (Record no. 29123)
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| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 7a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 180713b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9783319739083 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 005.275 |
| Item number | TAN |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Tanase, Alexandru-Petru |
| 245 ## - TITLE STATEMENT | |
| Title | Symbolic parallelization of ested loop programs |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Name of publisher, distributor, etc | Springer |
| Date of publication, distribution, etc | 2018 |
| Place of publication, distribution, etc | Switzerland |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xii, 176 p. |
| Dimensions | 23 cm. |
| 365 ## - TRADE PRICE | |
| Price type code | EUR |
| Price amount | 109.99/ Rs. 9096.17 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book introduces new compilation techniques, using the polyhedron model for the resource-adaptive parallel execution of loop programs on massively parallel processor arrays. The authors show how to compute optimal symbolic assignments and parallel schedules of loop iterations at compile time, for cases where the number of available cores becomes known only at runtime. The compile/runtime symbolic parallelization approach the authors describe reduces significantly the runtime overhead, compared to dynamic or just‐in-time compilation. The new, on‐demand fault‐tolerant loop processing approach described in this book protects loop nests for parallel execution against soft errors |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | COMPUTERS / Programming / Parallel |
| Topical term or geographic name as entry element | Computer architecture |
| Topical term or geographic name as entry element | Parallel programming (Computer science) |
| Topical term or geographic name as entry element | Engineering |
| Topical term or geographic name as entry element | Circuits and Systems |
| Topical term or geographic name as entry element | Processor Architectures |
| Topical term or geographic name as entry element | Electronics and Microelectronics, Instrumentation |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Hannig, Frank |
| Personal name | Teich, Jurgen |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Item type | Books |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Date acquired | Total Checkouts | Full call number | Barcode | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | DAU | DAU | 13/07/2018 | 005.275 TAN | 031581 | 13/07/2018 | Books |