| 000 -LEADER |
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| fixed length control field |
nam a22 7a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
190613b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780470828496 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.399 |
| Item number |
BAI |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Bailey, Donald G. |
| 245 ## - TITLE STATEMENT |
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| Title |
Design for embedded image processing on FPGAs |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Name of publisher, distributor, etc |
Wiley & Sons, |
| Date of publication, distribution, etc |
2011 |
| Place of publication, distribution, etc |
Singapore : |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
xvi, 482 p. : |
| Other physical details |
ill. ; |
| Dimensions |
25 cm. |
| 365 ## - TRADE PRICE |
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| Price amount |
170.00 |
| Price type code |
USD |
| Unit of pricing |
00 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
"Dr Donald Bailey starts with introductory material considering the problem of embedded image processing, and how some of the issues may be solved using parallel hardware solutions. Field programmable gate arrays (FPGAs) are introduced as a technology that provides flexible, fine-grained hardware that can readily exploit parallelism within many image processing algorithms. A brief review of FPGA programming languages provides the link between a software mindset normally associated with image processing algorithms, and the hardware mindset required for efficient utilization of a parallel hardware design. The design process for implementing an image processing algorithm on an FPGA is compared with that for a conventional software implementation, with the key differences highlighted. Particular attention is given to the techniques for mapping an algorithm onto an FPGA implementation, considering timing, memory bandwidth and resource constraints, and efficient hardware computational techniques. Extensive coverage is given of a range of low and intermediate level image processing operations, discussing efficient implementations and how these may vary according to the application. The techniques are illustrated with several example applications or case studies from projects or applications the author has been involved with. Issues such as interfacing between the FPGA and peripheral devices are covered briefly, as is designing the system in such a way that it can be more readily debugged and tuned. Provides a bridge between algorithms and hardware. Demonstrates how to avoid many of the potential pitfalls. Offers practical recommendations and solutions. Illustrates several real-world applications and case studies. Allows those with software backgrounds to understand efficient hardware implementation." |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Embedded computer systems |
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| Topical term or geographic name as entry element |
Field programmable gate arrays |
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| Topical term or geographic name as entry element |
Computer Engineering |
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| Topical term or geographic name as entry element |
Machine theory |
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| Topical term or geographic name as entry element |
Electronics |
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| Topical term or geographic name as entry element |
Microelectronics |
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| Topical term or geographic name as entry element |
Technology engineering |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
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| Item type |
Books |