| 000 -LEADER |
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| fixed length control field |
nam a22 7a 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
190527b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9780387938196 |
| Terms of availability |
(hbk) |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.3815 |
| Item number |
BHA |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Bhasker, J. |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Static timing analysis for nanometer designs : a practical approach |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Place of publication, distribution, etc |
New York : |
| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
2009 |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xx, 572 p. : |
| Other physical details |
ill. ; |
| Dimensions |
24 cm. |
| 365 ## - TRADE PRICE |
|---|
| Price type code |
EUR |
| Price amount |
199.99 |
| Unit of pricing |
00 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers."--Publisher's website. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Engineering |
|
|---|
| Topical term or geographic name as entry element |
Electrical |
|
|---|
| Topical term or geographic name as entry element |
Nanoelectromechanical systems |
|
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| Topical term or geographic name as entry element |
Timing circuits |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Chadha, Rakesh |
| Relator term |
aut |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
Books |