| 000 -LEADER | |
|---|---|
| fixed length control field | nam a22 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 210204b xxu||||| |||| 00| 0 eng d |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3819 |
| Item number | JAI |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Jain, Nupur |
| 245 ## - TITLE STATEMENT | |
| Title | Investigating into a light-weight reconfigurable VLSI architecture for biomedical signal processing applications |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) | |
| Place of publication, distribution, etc | Gandhinagar |
| Name of publisher, distributor, etc | Dhirubhai Ambani Institute of Information and Communication Technology |
| Date of publication, distribution, etc | 2019 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xix, 210 p. |
| 500 ## - GENERAL NOTE | |
| General note | Mishra, Biswajit, Thesis supervisor Student ID No. 201221008 Thesis (Ph.D.) -Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 2019 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | The Body Sensor Network systems consist of signal acquisition and processing blocks along with Power Management Unit and radio transmission capabilities. The high power consumption of the radio transmission is often eliminated by adopting the on-node processing through signal processing platform with increased computation ability. Dedicated hardware accelerators optimized for operations predominantly seen in biomedical signal processing algorithms are oftenused in tandem with a microprocessor for this purpose. However, they do not support further algorithm improvements and optimizations owing to their dedicated nature. The benefits of configurability can be found in reconfigurable architectures at the cost of reconfiguration overheads. The shift-accumulate architecture developed in this thesis leverage the regularity in dominant functions in biomedical signal processing and thereby yields gate count advantages. The configurable datapath of the architecture renders multiple DSP operation emulation by means of mapping methodologies developed for efficient realization in terms of hardware utilization and memory accesses. The architecture exhibits various topologies which further supports efficient function realization. The configuration scheme of the architecture is developed which effectively consist of control word and tightly coupled data memory. The architecture is realized on a Filed Programmable Gate Array (FPGA) platform demonstrating the target function emulation and hardware results are compared with ideal outcomes. The Video Graphics Array (VGA) and Universal Asynchronous Receiver Transmitter (UART) interface controllers are developed in this work for error quantification and analysis. The architecture contains a 66 array of functional units having shift-accumulate as its underlying operation and has gate count of 25k and 46.9 MHz operating frequency while emulating 36-tap FIR, CORDIC, DCT, DWT, moving average, squaring and differentiation functions. Generally, biomedical signal processing functions include multiple stages consisting of noise removal, feature detection and extraction etc. The on-the-fly reconfigurability is incorporated into the architecture that leverage the low input datarates of biosignals. The architecture reconfigures dynamically while realizing different functions of the signal chain. The memory adapts to the incoming target function and supports 7 functions in its present structure. However, the architecture and memory remains scalable. Pan-Tompkins Algorithm based QRS detection realization is demonstrated on the architecture using the reconfigurability. This work offers 4 reduced area and 2.3 increase in performance with respect to the existing contemporary literatures. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Computer circuits |
| Topical term or geographic name as entry element | Electronic digital computers |
| Topical term or geographic name as entry element | Integrated circuits |
| Topical term or geographic name as entry element | Very large scale integration |
| Topical term or geographic name as entry element | Computer architecture |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Mishra, Biswajit |
| 856 ## - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://drsr.daiict.ac.in/handle/123456789/892 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Thesis and Dissertations |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Permanent Location | Current Location | Date acquired | Full call number | Barcode | Date last seen | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|
| DAIICT | DAIICT | 2020-03-03 | 621.3819 JAI | T00831 | 2021-02-04 | Thesis and Dissertations |