| 000 -LEADER |
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| fixed length control field |
a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
221129b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9783030981112 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.395 |
| Item number |
CHA |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Chakravarthi, Veena S. |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
SoC physical design : a comprehensive guide |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Name of publisher, distributor, etc |
Springer International Publishing, |
| Date of publication, distribution, etc |
2022 |
| Place of publication, distribution, etc |
Cham : |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxiv, 155 p. ; |
| Other physical details |
ill., (Some Color) |
| Dimensions |
24 cm |
| 365 ## - TRADE PRICE |
|---|
| Unit of pricing |
99.99 |
| Price amount |
EUR |
| Price type code |
84.50 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
SoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC). The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Provides a comprehensive overview of the skills required for complex SoC design and development; Examines SOC design challenges in nanotechnology scales; Offers readers professional tricks to using tools for optimal design runs. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Circuits integres a tres grande echelle |
|
|---|
| Topical term or geographic name as entry element |
Integrated circuits Very large scale integration |
|
|---|
| Topical term or geographic name as entry element |
Systems on a chip Design |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Koteshwar, Shivananda R. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
Books |