| 000 -LEADER |
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| fixed length control field |
nam a22 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
240319b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783030692117 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.3815 |
| Item number |
HUH |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Huhn, Sebastian |
| 245 ## - TITLE STATEMENT |
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| Title |
Design for testability, debug and reliability : next generation measures using formal techniques |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
2021 |
| Place of publication, distribution, etc |
Cham : |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxi, 164 p. ; |
| Other physical details |
ill., |
| Dimensions |
23 cm |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
69.99 |
| Price type code |
€ |
| Unit of pricing |
93.50 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
This book introduces several novel approaches to pave the way for the next generation of integrated circuits, which can be successfully and reliably integrated, even in safety-critical applications. The authors describe new measures to address the rising challenges in the field of design for testability, debug, and reliability, as strictly required for state-of-the-art circuit designs. In particular, this book combines formal techniques, such as the Satisfiability (SAT) problem and the Bounded Model Checking (BMC), to address the arising challenges concerning the increase in test data volume, as well as test application time and the required reliability. All methods are discussed in detail and evaluated extensively, while considering industry-relevant benchmark candidates. All measures have been integrated into a common framework, which implements standardized software/hardware interfaces. Provides readers with a combination of a comprehensive set of formal techniques covering and enhancing different aspects of the state-of-the-art design and test flow for ICs; Introduces newly developed heuristic, formal optimization-based and partition-based retargeting techniques and integrates them into a common framework; Describes fully compliant (with respect to industrial de-facto standard) measures to enhance the DFT, DFD and DFR capabilities while supporting standardized data exchange formats; Includes new measures to tackle shortcomings of existing state-of-the-art methods, including zero-defect enforcing safety-critical applications. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Integrated circuits |
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| Topical term or geographic name as entry element |
Design and construction |
|
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| Topical term or geographic name as entry element |
Circuits Reliability |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Drechsler, Rolf |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
|
| Item type |
Books |