000 -LEADER |
fixed length control field |
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008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
fixed length control field |
250316b xxu||||| |||| 00| 0 eng d |
020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
International Standard Book Number |
9781119810452 |
Terms of availability |
(hbk) |
082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
Classification number |
006.3 |
Item number |
LIU |
100 ## - MAIN ENTRY--PERSONAL NAME |
Personal name |
Liu, Albert Chun-Chen |
245 ## - TITLE STATEMENT |
Title |
Artificial intelligence hardware design : challenges and solutions |
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
Name of publisher, distributor, etc |
Wiley-IEEE Press, |
Date of publication, distribution, etc |
2021 |
Place of publication, distribution, etc |
Hoboken : |
300 ## - PHYSICAL DESCRIPTION |
Extent |
xxii, 208 p. ; |
Other physical details |
ill.,(b & w), |
Dimensions |
24 cm. |
365 ## - TRADE PRICE |
Price amount |
118.95 |
Price type code |
$ |
Unit of pricing |
90.60 |
504 ## - BIBLIOGRAPHY, ETC. NOTE |
Bibliography, etc |
Includes bibliographical references and index. |
520 ## - SUMMARY, ETC. |
Summary, etc |
ARTIFICIAL INTELLIGENCE HARDWARE DESIGN Learn foundational and advanced topics in Neural Processing Unit design with real-world examples from leading voices in the field In Artificial Intelligence Hardware Design: Challenges and Solutions , distinguished researchers and authors Drs. Albert Chun Chen Liu and Oscar Ming Kin Law deliver a rigorous and practical treatment of the design applications of specific circuits and systems for accelerating neural network processing. Beginning with a discussion and explanation of neural networks and their developmental history, the book goes on to describe parallel architectures, streaming graphs for massive parallel computation, and convolution optimization. The authors offer readers an illustration of in-memory computation through Georgia Tech's Neurocube and Stanford's Tetris accelerator using the Hybrid Memory Cube, as well as near-memory architecture through the embedded eDRAM of the Institute of Computing Technology, the Chinese Academy of Science, and other institutions. Readers will also find a discussion of 3D neural processing techniques to support multiple layer neural networks, as well as information like: A thorough introduction to neural networks and neural network development history, as well as Convolutional Neural Network (CNN) models Explorations of various parallel architectures, including the Intel CPU, Nvidia GPU, Google TPU, and Microsoft NPU, emphasizing hardware and software integration for performance improvement Discussions of streaming graph for massive parallel computation with the Blaize GSP and Graphcore IPU An examination of how to optimize convolution with UCLA Deep Convolutional Neural Network accelerator filter decomposition Perfect for hardware and software engineers and firmware developers, Artificial Intelligence Hardware Design is an indispensable resource for anyone working with Neural Processing Units in either a hardware or software capacity. |
650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
Topical term or geographic name as entry element |
Artificial Intelligence |
|
Topical term or geographic name as entry element |
Computer Design and Construction |
|
Topical term or geographic name as entry element |
Parallel architectures |
|
Topical term or geographic name as entry element |
Streaming graphs |
|
Topical term or geographic name as entry element |
Convolution optimization |
|
Topical term or geographic name as entry element |
In-memory computation |
|
Topical term or geographic name as entry element |
Nea-memory Architecture |
|
Topical term or geographic name as entry element |
Network Sparsity |
|
Topical term or geographic name as entry element |
3D neural processing |
700 ## - ADDED ENTRY--PERSONAL NAME |
Personal name |
Law, Oscar Ming Kin |
942 ## - ADDED ENTRY ELEMENTS (KOHA) |
Source of classification or shelving scheme |
|
Item type |
Books |