| 000 -LEADER |
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| fixed length control field |
a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
250606b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9788132225195 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
620 |
| Item number |
PAL |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Palchaudhuri, Ayan |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
High Performance Integer Arithmetic Circuit Design on FPGA : Architecture, Implementation and Design Automation |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Name of publisher, distributor, etc |
Springer India, |
| Date of publication, distribution, etc |
2016 |
| Place of publication, distribution, etc |
New Delhi : |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvii, 114 p. ; |
| Other physical details |
ill., |
| Dimensions |
25 cm |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
99.99 |
| Price type code |
€ |
| Unit of pricing |
100.40 |
| 490 ## - SERIES STATEMENT |
|---|
| Series statement |
Springer Series in Advanced Microelectronics, 1437-0387 ; |
| Volume number/sequential designation |
v.51 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references at the end of each chapters and index. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Absolute difference circuit |
|
|---|
| Topical term or geographic name as entry element |
Barrel shifter |
|
|---|
| Topical term or geographic name as entry element |
Carry chain |
|
|---|
| Topical term or geographic name as entry element |
Cellular Automata |
|
|---|
| Topical term or geographic name as entry element |
DSP slice |
|
|---|
| Topical term or geographic name as entry element |
Datapath Circuits |
|
|---|
| Topical term or geographic name as entry element |
Controlpath Circuits |
|
|---|
| Topical term or geographic name as entry element |
Linear Cellular Automata |
|
|---|
| Topical term or geographic name as entry element |
Design Automation |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Chakraborty, Rajat Subhra |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Item type |
Books |