| 000 -LEADER |
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| fixed length control field |
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| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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250611b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783030964177 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621.395 |
| Item number |
KAH |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Kahng, Andrew B. |
| 245 ## - TITLE STATEMENT |
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| Title |
VLSI physical design : from graph partitioning to timing closure |
| 250 ## - EDITION STATEMENT |
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| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
2022. |
| Place of publication, distribution, etc |
Cham : |
| 300 ## - PHYSICAL DESCRIPTION |
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| Extent |
xvii, 317 p. ; |
| Other physical details |
ill., (some col.), |
| Dimensions |
23 cm. |
| 365 ## - TRADE PRICE |
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| Price amount |
59.99 |
| Price type code |
€ |
| Unit of pricing |
100.40 |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
Include bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Computer-aided design |
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| Topical term or geographic name as entry element |
Integrated circuits |
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| Topical term or geographic name as entry element |
Very large scale integration |
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| Topical term or geographic name as entry element |
Design and construction |
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| Topical term or geographic name as entry element |
Timing circuits |
| 700 ## - ADDED ENTRY--PERSONAL NAME |
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| Personal name |
Lienig, Jens |
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| Personal name |
Markov, Igor L. |
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| Personal name |
Hu, Jin |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
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| Item type |
Books |