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| fixed length control field |
a |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
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| fixed length control field |
250718b xxu||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
9783031180224 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
004.22 |
| Item number |
GOO |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
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| Personal name |
Goossens, Bernard |
| 245 ## - TITLE STATEMENT |
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| Title |
Guide to computer processor architecture : a RISC-V approach, with high-level synthesis |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
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| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
2023 |
| Place of publication, distribution, etc |
Cham : |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxv, 438 p. ; |
| Other physical details |
ill., (some col.), |
| Dimensions |
24 cm |
| 365 ## - TRADE PRICE |
|---|
| Price amount |
54.99 |
| Price type code |
€ |
| Unit of pricing |
100.30 |
| 490 ## - SERIES STATEMENT |
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| Series statement |
Undergraduate topics in computer science |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
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| Bibliography, etc |
Includes bibliographical references and index. |
| 520 ## - SUMMARY, ETC. |
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| Summary, etc |
This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
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| Topical term or geographic name as entry element |
Computer architecture |
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|---|
| Topical term or geographic name as entry element |
RISC microprocessors |
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| Topical term or geographic name as entry element |
Operating systems |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
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| Source of classification or shelving scheme |
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| Item type |
Books |