Scalable hardware verification with symbolic simulation
By: Bertacco, Valeria.
Material type:
BookPublisher: New York: Springer, 2006Description: xx, 177 p.; ill., index: 24 cm.ISBN: 9780387244112 .Subject(s): Computer networks -- Scalability | Computer simulation | Integrated circuits -- Verification | Integrated circuits -- Verification -- Simulation methods | System design -- Simulation methodsDDC classification: 621.392
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
| Books | 621.392 BER (Browse shelf) | Available | 014569 |
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| 621.392 ASH Designer's guide to VHDL | 621.392 ASH Designer's guide to VHDL | 621.392 BEN Principles of verifiable RTL design : a functional coding style supporting verification processes in verilog | 621.392 BER Scalable hardware verification with symbolic simulation | 621.392 BER Hardware/Software Co-Design and Co-Verification | 621.392 BHA System verilog primer | 621.392 BHA A VHDL synthesis primer |
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