Routing congestion in VLSI circuits : estimation and optimization
By: Saxena, Prashant.
Contributor(s): Sapatnekar, Sachin S | Shelar, Rupesh S.
Material type:
BookSeries: Series on integrated circuits and systems.Publisher: New York: Springer, 2007Description: xiv, 248 p.; ill.: 24 cm.ISBN: 9780387300375 .Subject(s): Integrated circuits -- Very large scale integration | Routing (Computer network management)DDC classification: 621.395
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
| Books | 621.395 SAX (Browse shelf) | Available | 017340 |
Browsing DAIICT Shelves Close shelf browser
| 621.395 SAL Digital Systems Design and Prototyping | 621.395 SAP Timing | 621.395 SAS Switching theory for logic synthesis. | 621.395 SAX Routing congestion in VLSI circuits : estimation and optimization | 621.395 SHA Logic Circuit Design | 621.395 SHE Routing in the third dimension : from VLSI chips to MCMs | 621.395 SHE Algorithms for VLSI physical design automation |
There are no comments for this item.