Design of prominent floating point multiplier using single electron transistor operating at room temperature
By: Trivedi, Rachesh.
Contributor(s): Banik, Sanghamitra | Parekh, Rutu | Agrawal, Yash.
Material type:
BookPublisher: Gandhinagar Dhirubhai Ambani Institute of Information and Communication Technology 2019Description: vi, 27 p.Subject(s): SET based device | FINFET CMOS technology | TDCDDC classification: 621.3815 Online resources: Click here to access online Summary: This project work has two main objectives. First is to introduce SET based device in digital logic circuit design. SET based devices has tremendous potential for the exploration to improve the current CMOS based device. The other objective is to implement 8bit,16bit and 32bit floating point multiplier. Performance analysis of and comparison of SET based floating point multiplier has been done with 16nm technology.An efficient floating point multiplier based on single electron transistor is proposed in this work. The aim is to work beyond CMOS technology and current trending research area in Nano-electronics.
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
| Thesis and Dissertations | 621.3815 TRI (Browse shelf) | Available | T00796 |
Parekh, Rutu; Agrawal, Yash, Thesis supervisor
Student ID no. 201711039; 201711041
Thesis (M.Tech.) -Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 2008
This project work has two main objectives. First is to introduce SET based device in digital logic circuit design. SET based devices has tremendous potential for the exploration to improve the current CMOS based device. The other objective is to implement 8bit,16bit and 32bit floating point multiplier. Performance analysis of and comparison of SET based floating point multiplier has been done with 16nm technology.An efficient floating point multiplier based on single electron transistor is proposed in this work. The aim is to work beyond CMOS technology and current trending research area in Nano-electronics.
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