000			00478nam a2200157Ia 4500
008			161214s9999 xx 000 0 und d
020			_a0471441481 _c(hbk)
082			_223 _a621.392 _bPAD
100			_aPadmanabhan, T. R.
245		0	_aDesign through Verilog HDL
260			_aNew Jersey: _bIEEE Press, _c2003
300			_axii, 455 p.; _bill., index: _c24 cm.
650			_aVerilog -Computer hardware description language
700			_aTripura Sundari, B. Bala.
942			_2ddc _cBK
999			_c2660 _d2660