000			nam a22 7a 4500
999			_c29075 _d29075
008			180728b xxu||||| |||| 00| 0 eng d
020			_a9789400795075
082			_a621.392 _bROG
100			_aRogin, Frank
245			_aDebugging at the electronic system level
260			_bSpringer, _c2010 _aDordrecht:
300			_axix, 199 p. : _bill.; _c24 cm.
365			_aEURO _b112.14
520			_aDebugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding
650			_aSystems engineering
650			_aDebugging in computer science
650			_aIntegrated circuits
650			_aHardware
650			_aDynamic program slicing
650			_aESL Design
650			_aSystemC Models
650			_aComputer hardware description languages
650			_aComputer software
650			_aMachine Theory
650			_aComputer Engineering
700			_aDrechsler, Rolf
942			_2ddc _cBK