000			nam a22 7a 4500
999			_c29564 _d29564
008			190527b xxu||||| |||| 00| 0 eng d
020			_a9780387938196 _c(hbk)
082			_a621.3815 _bBHA
100			_aBhasker, J.
245			_aStatic timing analysis for nanometer designs : a practical approach
260			_aNew York : _bSpringer, _c2009
300			_axx, 572 p. : _bill. ; _c24 cm.
365			_aEUR _b199.99 _d00
504			_aIncludes bibliographical references and index.
520			_aStatic Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats. This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful. Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers."--Publisher's website.
650			_aEngineering
650			_aElectrical
650			_aNanoelectromechanical systems
650			_aTiming circuits
700			_aChadha, Rakesh _eaut
942			_2ddc _cBK