000			nam a22 7a 4500
999			_c30236 _d30236
008			210204b xxu||||| |||| 00| 0 eng d
082			_a621.382 _bKAS
100			_aKasodniya, Sanjay Kumar
245			_aInvestigation into radiation hardening techniques on differential receiver and power management unit in 0.8um CMOS for space applications
260			_aGandhinagar _bDhirubhai Ambani Institute of Information and Communication Technology _c2019
300			_ax, 123 p.
500			_aMishra, Biswajit, Thesis supervisor Student ID No. 201121010 Thesis (Ph.D.) -Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 2019
520			_aThis report details out radiation hardening techniques, their implementation on Dierential Receiver and Power Management Unit. Dierential Receiver ASIC is designed with addressable, synchronous and asynchronous features called dressableSynchronous/asynchronous Dierential Receiver (ASDR) ASIC. Onboard Payload data handling subsystems use standard bus interfaces (RS422) and protocols (eg. UART) and are available in separate devices. The proposed ASDR implements the RS422 electrical interface for dierential-serial-data reception and has multi-mode synchronous asynchronous serial data handling protocol, as a single chip solution. The design has 5 bit self-address feature, which is useful if these devices are used in multi-drop conguration. Such a single chip solution is of importance for ground based application, in space and related applications. This design is fabricated with 0.18m CMOS process. Radiation hardening techniques, guard-ring, node-splitting and dierential-charge-cancellation have been implemented in the ASIC. After fabrication, the dierential receiver ASIC has been tested for radiation environment specic to Single Event Eects and Total Ionizing Dose, with an aim to make it suitable for space applications. To the best of our knowledge this is the rst ever integrated chip that provide interface (both Tx and Rx conguration) with protocol (UART and synchronous serial to parallel) for low speed dierential data communication. A capacitive power management unit (PMU) for a DC energy harvester such as a photovoltaic (PV) is proposed. It is assumed that the input will have a minimal voltage requirement of approximately 460mV and can go up to 800mV , typical output from a PV cell. This is our initial attempt to design a novel PMU based on standard 0:18m CMOS models to be used for applications (WSN, payload sensors) that require energy autonomy. Power management unit is designed to interface logic circuit with energy harvesters. Radiation hardening technique is used to make this design suitable for space applications. The temperature sensing system on a satellite can use ASDR and PMU for wired and wireless approach respectively.
650			_aPower Management Unit
650			_aCMOS
650			_aRadiation hardening techniques
700			_aMishra, Biswajit
856			_uhttp://drsr.daiict.ac.in/handle/123456789/889
942			_cTD