000			nam a22 4500
999			_c30251 _d30251
008			210205b xxu||||| |||| 00| 0 eng d
082			_a621.3815 _bTRI
100			_aTrivedi, Rachesh
245			_aDesign of prominent floating point multiplier using single electron transistor operating at room temperature
260			_aGandhinagar _bDhirubhai Ambani Institute of Information and Communication Technology _c2019
300			_avi, 27 p.
500			_aParekh, Rutu; Agrawal, Yash, Thesis supervisor Student ID no. 201711039; 201711041 Thesis (M.Tech.) -Dhirubhai Ambani Institute of Information and Communication Technology, Gandhinagar, 2008
520			_aThis project work has two main objectives. First is to introduce SET based device in digital logic circuit design. SET based devices has tremendous potential for the exploration to improve the current CMOS based device. The other objective is to implement 8bit,16bit and 32bit floating point multiplier. Performance analysis of and comparison of SET based floating point multiplier has been done with 16nm technology.An efficient floating point multiplier based on single electron transistor is proposed in this work. The aim is to work beyond CMOS technology and current trending research area in Nano-electronics.
650			_aSET based device
650			_aFINFET CMOS technology
650			_aTDC
700			_aBanik, Sanghamitra
700			_aParekh, Rutu
700			_aAgrawal, Yash
856			_uhttp://drsr.daiict.ac.in/handle/123456789/876
942			_cTD