000			a
999			_c30949 _d30949
008			220610b xxu||||| |||| 00| 0 eng d
020			_a9783030797737
082			_a004.22 _bWIJ
100			_aWijtvliet, Mark
245			_aBlocks, towards energy-efficient, coarse-grained reconfigurable architectures
260			_bSpringer, _c2022 _aCham :
300			_ax, 220 p. : _bill., _c25 cm
365			_b84.99 _cEUR _d86.00
504			_aInclude bibliographic references and index.
520			_aThis book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs. The book starts with an extensive evaluation of historic and existing CGRAs and their strengths and weaknesses. This also leads to a better understanding and new definition of what distinguishes CGRAs from other architectural approaches. The authors introduce Blocks as unique due to its separate programmable control and data paths, allowing light-weight instruction decode units to be arbitrarily connected to one or more functional units (FUs) over a statically configured interconnect. The discussion includes an explanation of how to model architectures, resulting in an area and energy model for Blocks. The accuracy of this model is evaluated against fully implemented architectures, showing that although it is three orders of magnitude faster than synthesis the error margin is very acceptable. The book concludes with a case study on a real System-on-Chip, including a RISC architecture, the Blocks CGRA and peripherals. Provides a comprehensive overview of many coarse-grained reconfigurable architectures (CGRAs) proposed in the last 25 years, as well as a classification of those CGRAs; Offers a new view on the positioning of CGRAs; Provides an in-depth description of structure of the Blocks CGRA and its unique aspects; Includes an extensive evaluation of various performance aspects of Blocks, such as performance, energy and area, as well as a comparison with various traditional approaches; Uses a case study showing how Blocks can be used in a real system on-chip, and how performance of this system-on-chip can be estimated using the proposed model.
650			_aAdaptive computing systems
650			_aComputer architecture
650			_aMicroprocessors
650			_aElectronic circuits
650			_aApplication specific processors (ASPs)
650			_a ARM Cortex-MO
650			_a Bit stream
650			_a Brain Sense
650			_aControl network
650			_aFunction Units(FUs)
650			_aGlobal memory
650			_aInstruction memories
650			_aNet-list
650			_aReconfigurable fabric
650			_aSwitch-boxes
650			_a Tool-flow
650			_a Virtual architecture
650			_a CERA
700			_aCorporaal, Henk
700			_aKumar, Akash
942			_2ddc _cBK