000			a
999			_c33011 _d33011
008			240318b xxu||||| |||| 00| 0 eng d
020			_a9783031791932
082			_a004.16 _bGOG
100			_aGogte, Vaibhav
245			_aA primer on memory persistency
260			_bSpringer, _c2022 _aCham :
300			_axix, 95 p. ; _bill., (some col.), _c24 cm
365			_b93.50 _c€ _d93.50
490			_aSynthesis Lectures on Computer Architecture, _v1935-3243
504			_aIncludes bibliographical references.
520			_aThis book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures and program crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
650			_aUndo logging
650			_aPersist order
650			_aSequential consistency
650			_aFailure atomicity
650			_aHardware Mechanism
650			_aMemory persistency models
650			_aPersistent Memories
700			_aKolli, Aasheesh
700			_aWenisch, Thomas F.
942			_2ddc _cBK