000			a
999			_c33048 _d33048
008			240319b xxu||||| |||| 00| 0 eng d
020			_a9783030576813
082			_a005.133 _bSON
100			_aSoni, Deepraj
245			_aHardware architectures for post-quantum digital signature schemes
260			_bSpringer, _c2021 _aCham :
300			_axxii, 170 p. ; _bill., _c25 cm.
365			_b99.99 _c€ _d93.50
504			_aIncludes bibliographical references and index.
520			_aThis book explores C-based design, implementation, and analysis of post-quantum cryptography (PQC) algorithms for signature generation and verification. The authors investigate NIST round 2 PQC algorithms for signature generation and signature verification from a hardware implementation perspective, especially focusing on C-based design, power-performance-area-security (PPAS) trade-offs and design flows targeting FPGAs and ASICs. Describes a comprehensive set of synthesizable c code base as well as the hardware implementations for the different types of PQC algorithms including lattice-based, code-based, and multivariate-based; Demonstrates the hardware (FPGA and ASIC) and hardware-software optimizations and trade-offs of the NIST round 2 signature-based PQC algorithms; Enables designers to build hardware implementations that are resilient to a variety of side-channels.
650			_aComputer algorithms
650			_aQuantum computing
650			_aArea overhead
650			_aBaseline implementation
650			_a Dynamic memory allocation
650			_aHash function
650			_aLoop unrolling
650			_aSecret key
650			_aSignature verification
650			_aUnrolling and loop
700			_aBasu, Kanad
700			_aNabeel, Mohammed
700			_aAaraj, Najwa
700			_aManzano, Marc
700			_aKarri, Ramesh
942			_2ddc _cBK