000 a
999 _c34016
_d34016
008 250606b xxu||||| |||| 00| 0 eng d
020 _a9788132225195
082 _a620
_bPAL
100 _aPalchaudhuri, Ayan
245 _aHigh Performance Integer Arithmetic Circuit Design on FPGA : Architecture, Implementation and Design Automation
260 _bSpringer India,
_c2016
_aNew Delhi :
300 _axvii, 114 p. ;
_bill.,
_c25 cm
365 _b99.99
_c
_d100.40
490 _aSpringer Series in Advanced Microelectronics, 1437-0387 ;
_vv.51
504 _aIncludes bibliographical references at the end of each chapters and index.
520 _aThis book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students, and professionals engaged in the domain of FPGA circuit optimization and implementation.
650 _aAbsolute difference circuit
650 _aBarrel shifter
650 _aCarry chain
650 _aCellular Automata
650 _aDSP slice
650 _aDatapath Circuits
650 _aControlpath Circuits
650 _aLinear Cellular Automata
650 _aDesign Automation
700 _aChakraborty, Rajat Subhra
942 _2ddc
_cBK