000			a
999			_c34120 _d34120
008			250611b xxu||||| |||| 00| 0 eng d
020			_a9783030964177
082			_a621.395 _bKAH
100			_aKahng, Andrew B.
245			_aVLSI physical design : from graph partitioning to timing closure
250			_a2nd ed.
260			_bSpringer, _c2022. _aCham :
300			_axvii, 317 p. ; _bill., (some col.), _c23 cm.
365			_b59.99 _c€ _d100.40
504			_aInclude bibliographical references and index.
520			_aDesign and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact. "VLSI Physical Design: From Graph Partitioning to Timing Closure" introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.
650			_aComputer-aided design
650			_aIntegrated circuits
650			_aVery large scale integration
650			_aDesign and construction
650			_aTiming circuits
700			_aLienig, Jens
700			_aMarkov, Igor L.
700			_aHu, Jin
942			_2ddc _cBK