000			a
999			_c34437 _d34437
008			250718b xxu||||| |||| 00| 0 eng d
020			_a9783031180224
082			_a004.22 _bGOO
100			_aGoossens, Bernard
245			_aGuide to computer processor architecture : a RISC-V approach, with high-level synthesis
260			_bSpringer, _c2023 _aCham :
300			_axxv, 438 p. ; _bill., (some col.), _c24 cm
365			_b54.99 _c€ _d100.30
490			_aUndergraduate topics in computer science
504			_aIncludes bibliographical references and index.
520			_aThis unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.
650			_aComputer architecture
650			_aRISC microprocessors
650			_aOperating systems
942			_2ddc _cBK