000			00697nam a2200217Ia 4500
008			161214s9999 xx 000 0 und d
020			_a0792373685 _c(hbk)
082			_223 _a621.395 _bBEN
100			_aBening, Lionel
245		0	_aPrinciples of Verifiable RTL Design : a functional coding style supporting verification processes in verilog
250			_a2nd ed.
260			_aBoston: _bKluwer Academic Publishers, _c2001
300			_a281 p.; _bill., index.: _c24 cm.
650			_aComputer Aided Design
650			_aIntegrated Circuits
650			_aVerifiable RTL Design
650			_aVerilog
650			_aVery Large Scale Integration
700			_aFoster, Harry D.
942			_2ddc _cBK
999			_c3965 _d3965