000			00527nam a2200169Ia 4500
008			161214s9999 xx 000 0 und d
020			_a0139773983 _c(hbk)
082			_223 _a621.392 _bCIL
100			_aCiletti, Michael D.
245		0	_aModeling, synthesis, and rapid prototyping with the verilog HDL
260			_aNew Jersey: _bPrentice Hall, _c1999
300			_a724 p.; _bill., index: _c24 cm.
650			_aHDL
650			_aRapid prototyping
650			_aVerilog (Computer hardware description language)
942			_2ddc _cBK
999			_c700 _d700