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Formal semantics and proof techniques for optimizing VHDL models

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BookPublisher: Boston: Kluwer Academic Publishers, 1999Description: xvi, 158 p.; ill.: 24 cm.ISBN: 0792383753 .Subject(s): VHDL (Computer hardware description language)DDC classification: 621.392

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Item type	Current location	Call number	Status	Date due	Barcode
Books		621.392 UMA (Browse shelf)	Available		013995

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Previous	621.392 SUT Verilog PLI handbook : a user's guide and comprehensive reference on the Verilog programming language interface	621.392 THO Verilog hardware description languages	621.392 THO Verilog hardware description languages	621.392 UMA Formal semantics and proof techniques for optimizing VHDL models	621.392 WIR Digital circuit design for computer science students : an introductory textbook	621.392 YAL VHDL : a starter's guide	621.392 ZEI Verilog Designer's Library	Next

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