Log in

Normal view MARC view ISBD view

Chip design for submicron VLSI : CMOS layout and simulation

By: Uyemura, John P.

Material type: materialTypeLabel

materialTypeLabel

BookPublisher: Australia: Thomson, 2007Description: xvi, 411 p.; ill.: 25 cm.ISBN: 8131501957 .Subject(s): Metal oxide semiconductors, Complementary -- Design and construction | Integrated circuits -- Very large scale integration -- Design and construction | MicrowindDDC classification: 621.3815

Tags from this library: No tags from this library for this title. Log in to add tags.

Holdings ( 2 )
Comments ( 0 )

Item type	Current location	Call number	Status	Date due	Barcode
CD-DVDs		621.3815 UYE (Browse shelf)	Available		C01321
Books		621.3815 UYE (Browse shelf)	Available		016547

Browsing DAIICT Shelves Close shelf browser

Previous		No cover image available						Next
Previous	621.3815 TOU Analogue IC design : the current-mode approach	621.3815 TRI Design of prominent floating point multiplier using single electron transistor operating at room temperature	621.3815 UYE Chip design for submicron VLSI : CMOS layout and simulation	621.3815 UYE Chip design for submicron VLSI : CMOS layout and simulation	621.3815 VAS Thermal and power management of integrated circuits	621.3815 VAS ESD design for analog circuits	621.3815 VAS Basic electronic circuits : problems and solutions	Next

There are no comments for this item.

Log in to your account to post a comment.

Powered by Koha