gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits : the semi-empirical and compact model approaches
By: Jespers, Paul G.
Material type:
BookSeries: Analog circuits and signal processing.Publisher: Dordrecht: Springer, 2010Description: xvi, 171 p.; ill.: 24 cm.ISBN: 9780387471006 .Subject(s): Metal oxide semiconductors, Complementary -- Design and construction | Linear integrated circuits -- Design and construction | Low voltage integrated circuits -- Design and constructionDDC classification: 621.3815
| Item type | Current location | Call number | Status | Date due | Barcode |
|---|---|---|---|---|---|
| Books | 621.3815 JES (Browse shelf) | Available | 025584 |
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| 621.3815 JAE Introduction to microelectronic fabrication, Volume 5 | 621.3815 JAE Microelectronic circuit design | 621.3815 JAV Carbon nanotube electronics | 621.3815 JES gm/ID design methodology, a sizing tool for low-voltage analog CMOS circuits : the semi-empirical and compact model approaches | 621.3815 JOH Unique chips and systems | 621.3815 JOH Analog integrated circuit design | 621.3815 JOH Analog integrated circuit design |
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